integrated circuit systems, inc. general description features ICS9147-14 block diagram pentium is a trademark of intel corporation frequency generator & integrated buffers for pentium/pro tm 9147-14 rev b 071897p ? four copies of cpu clock ? twelve sdram (3.3 v ttl), usable as agp clocks ? seven copies of pciclk clock (synchronous with cpu clock/2 or cpu/2.5 for 75 and 83.3 mhz cpu) ? cpu clocks to pciclk clocks skew 1-4ns, center 2.6ns. ? one ioapic clock @14.31818 mhz ? two copies of ref. clock @14.31818 mhz ? ref. 14.31818 mhz xtal oscillator input ? separate v ddl1 for four cpu and single ioapic output buffers to allow 2.5v output (or std. vdd) ? one each 48/ 24 mhz (3.3 v ttl) ? 3.3v outputs: sdram, pci, ref, 48/24mhz. ? 2.5v or 3.3v outputs: cpu, ioapic. ? 20 ohm cpu clock output impedance ? 20 ohm pci clock output impedance ? 1.5ns rise time (30 pf loading) ? 250 ps cpu, pci clock skew ? 350ps (cycle by cycle) cpu jitter ? 2ms power up clock stable time ? 45-55% clock duty cycle ? 48 pin 300 mil ssop package ? 3.0v ? 3.7v supply range w/2.5v compatible outputs the ICS9147-14 generates all clocks required for high speed risc or cisc microprocessor systems such as intel pentiumpro. two bidirectional i/o pins (fs1,fs2) are latched at power-on to the functionality table, with fs0 selectable in real-time to toggle between conditions. high drive pciclk and sdram outputs typically provide greater than 1 v/ns slew rate into 30 pf loads. cpu outputs typically provide better than 1v/ns slew rate into 20 pf loads while maintaining 50 5% duty cycle. the ref clock outputs typically provide better than 0.5v/ns slew rates. seperate buffers supply pins vddl1 allow for 3.3v or reduced voltage swing (from 2.9 to 2.5v) for cpu (0:3) and ioapic outputs. pin configuration 48-pin ssop power groups vdd1 = ref (0:1), x1, x2, 24mhz, 48mhz vdd2 = pciclkf, pciclk(0:5) vdd3 = sdram (0;11) vddl1 = cpuclk (0:3) * internal pull-up resistor of 300k to 3.3v on indicated inputs ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ICS9147-14 pin descriptions functionality 3.3v10% 0-70c crystal (x1, x2 = 14.3181mhz fs2 fs1 fs0 cpu, sdram(mhz) pciclk (mhz) ref, ioapic (mhz) 0 0 0 50.0 25.0 14.318 0 0 1 75.0 32.0 14.318 0 1 0 33.3 16.65 14.318 0 1 1 68.5 34.25 14.318 1 0 0 55.0 27.5 14.318 1 0 1 75.0 37.5 14.318 1 1 0 60.0 30.0 14.318 1 1 1 66.8 33.4 14.318 * internal pull-up resistor of 120k to 3.3v on indicated inputs pin number pin name type description 1 vdd1 pwr ref (0:2), xtal, 24mhz, 48mhz power supply 2 ref0 out 14.318 mhz reference clock. 3,9,22,33,39,45 gnd pwr ground 4x1 in crystal input has internal load cap and feedback resistor from x2 5 x2 out crystal output nominally 14.318mhz. has internal load cap 16,23,24, 27,48 n/c - pins are not internally connected 6,14 vdd2 pwr supply for pciclk_f and pciclk (0:5) 7 pciclk_f out free running pci clock fs1* in frequency select pin. * 8 pciclk0 out pci clock output. fs2* in frequency select pin. * 10, 11, 12, 13 pciclk(1:4) out pci clock outputs 15 pciclk5 out pci clock output. 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38 sdram (0:11) out sdram clock outputs. 19,30,36 vdd3 pwr supply for sdram (0:11) 25 24mhz out 24mhz output clock 26 48mhz out 48mhz output clock fs0* in frequency select pin 40, 41, 43, 44 cpuclk(0:3) out cpu clock outputs, powered by vdd1 42 vddl1 pwr supply for cpu (0:3) and ioapic clock, can be 2.5 or 3.3v 46 ref1 out 14.318 mhz reference clock. 47 ioapic out ioapic clock output. powered by vddl1.
3 ICS9147-14 absolute maximum ratings electrical characteristics at 3.3v supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage t emperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il latched inputs - - 0.8 v input high voltage v ih latched inputs 2.0 - - v output low current 1 i ol1 vol=0.8v; for sdram, pciclk 19.0 30.0 - ma output high current 1 i oh1 voh=2.0v; for sdram pciclk - -26.0 -16.0 ma output low current 1 i ol2 vol=0.8v; 24, 48 clks, cpu, ref & ioapic 16.0 25.0 - ma output high current 1 i oh2 voh=2.0v; 24, 48 clks, cpu, ref & ioapic - -22.0 -14.0 ma output low current 1 i ol3 vol=0.8v; for cpu at vddl = 2.5v 10.0 18.0 - ma output high current 1 i oh3 voh = 1.7v; for cpu at vddl = 2.5v - -14.0 -8.0 ma output low voltage 1 v ol1 iol = 10ma; for pciclk, sdram -0.30.4v output high voltage 1 v oh1 ioh = -10ma; for sdram, pciclk 2.4 2.8 - v output low voltage 1 v ol2 iol = 8ma; for fixed clks, cpu, ref & ioapic -0.30.4v output high voltage 1 v oh2 ioh = -8ma; for fixed clks, cpu, ref & ioapic 2.4 2.8 - v output low voltage 1 v ol3 iol = 5ma; for cpu at vddl = 2.5v - 0.25 0.4 ma output high voltage 1 v oh3 ioh = -5ma; for cpu at vddl = 2.5v 2.1 2.25 - ma supply current i dd @66.6 mhz; all outputs unloaded - 70 120 ma pullup resistor 1 r pu1 fs0, fs1 fs2 inputs 150 300 450 k ohm
4 ICS9147-14 electrical characteristics at 3.3v v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units rise time 1 t r1 20pf load, 0.8 to 2.0v cpu, ioapic, fixed & ref -0.91.5ns fall time 1 t f1 20pf load, 2.0 to 0.8v cpu, ioapic, fixed & ref -0.81.4 ns rise time 1 t r2 20pf load, 20% to 80% cpu, ioapic, fixed & ref -1.52.5ns fall time 1 t f2 20pf load, 80% to 20% cpu, ioapic, fixed& ref -1.42.4 ns rise time 1 t r3 20pf load, 0.8 to 2.0v pci, sdram - 0.9 1.5 ns fall time 1 t f3 20pf load, 2.0 to 0.8v pci, sdram - 0.8 1.4 ns rise time 1 t r4 20pf load, 0.4 to 2.0v , cpu and ioapic with vddl = 2.5v --3.0 ns fall time 1 t f4 20pf load, 2.0 to 0.4v, cpu and ioapic with vddl = 2.5v --2.0 ns duty cycle 1 d t 20pf load @ vout=1.4v all clocks except ref 45 50 55 % duty cycle 1 d t2 20pf load @ vout=1.4v ref outputs 40 50 60 % jitter, one sigma 1 t jis1 cpu & pciclk clocks; load=20pf, sdram; load = 30pf - 50 150 ps jitter, absolute 1 t jab1 cpu & pciclk clocks; load=20pf, sdram; load = 30pf -250 - 250 ps jitter, cycle to cycle t jc-c cpu - 200 350 ps jitter, one sigma 1 t jis2 fixed clk; load=20pf - 1 3 % jitter, absolute 1 t jab2 fixed clk; load=20pf -5 2 5 % input frequency 1 f i 12.0 14.318 16.0 mhz logic input capacitance 1 c in logic input pins - 5 - pf crystal oscillator capacitance 1 c inx x1, x2 pins - 18 - pf power-on time 1 t on from vdd=1.6v to 1st crossing of 66.6 mhz vdd supply ramp < 40ms -2.54.5 ms clock skew 1 t sk1 cpu to cpu or pci to pci; load=20pf; @1.4v (same vdd) - 150 250 ps clock skew 1 t sk2 sdram to sdram; load=20pf; @1.4v - 300 500 ps clock skew 1 t sk3 cpu to pciclk; load=20pf; @1.4v (cpu is early) 1 2.1 4 ns
5 ICS9147-14 pins 7, 8 and 26 on the ICS9147-14 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm(10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. shared pin operation - input/output pins figs. 1 and 2 show the recommended means of implementing this function. in fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device?s internal logic. figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. these figures illustrate the optimal pcb physical layout options. these configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. the layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s). fig. 1
6 ICS9147-14 fig. 2a fig. 2b
7 ICS9147-14 ssop package ordering information ics9147f-14 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device t ype (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp symbol common dimensions variations d n min. nom. max. min. nom. max. a .095 .101 .110 ac .620 .625 .630 48 a1 .008 .012 .016 a2 .088 .090 .092 b .008 .010 .0135 c.005- .010 d see variations e .292 .296 .299 e0.025 bsc h .400 .406 .410 h .010 .013 .016 l .024 .032 .040 n see variations 0 5 8 x .085 .093 .100 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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